A gate dielectric or an interfacial oxide layer is a very sensitive component of a semiconductor device, and requirements of appropriate dielectric layers include high dielectric breakdown strength, low leakage current, good diffusion barrier properties, low trapping densities and low interfacial states. As device dimensions decrease, the requirements become more stringent and a lower thickness of an interfacial oxide layer is needed to meet the more stringent requirements.
In the conventional chemical oxidation process performed for formation of an interfacial oxide layer, solution containing ozone is commonly used. However, ozone solution always saturates at about 7 angstroms and the interfacial oxide layer encounters a difficulty that the thickness of the interfacial oxide layer cannot be produced below 7 angstroms by chemical oxidation alone. Thus an etching process is necessary to be performed following the chemical oxidation process.
Cleaning solution of Standard Clean 1 (hereinafter SC1 solution) is conventionally used for cleaning or light etching oxide of a surface of a semiconductor element. However, even SC1 solution has a low etching rate to most semiconductor manufacturing materials; it is still difficult to reach desired thickness of the interfacial oxide layer by controlling time of processing. Thus, mixture containing ozone and SC1 solution is then to be used for growing and etching back oxide for better control of thickness (self-saturated etching process) instead of only using SC1 solution.
The inventor has found that ammonium contained in SC1 solution is able to penetrate through the interfacial oxide layer during processing, damage silicon surface underneath the interfacial oxide layer and increase roughness of the silicon surface, and the product with bad negative-bias temperature instability (NBTI) is produced. Yet, the process of etching back has to be performed after formation of the interfacial oxide layer in order to produce an interfacial oxide layer with lower thickness due to a market trend of miniaturization, otherwise an interfacial oxide layers is not able to be lower than 7 angstroms in thickness and the device encounters a situation of high performance without alternation of small sizes.
Accordingly, it is needed to provide a method to thin down the interfacial oxide layer for achieving market trend miniaturization without reduction in performance of the devices. The inventor of the present invention based on years of experience on related research and development has invented a method of interfacial oxide layer formation to improve yields, performance and stability of product performance, and most importantly, thin down the interfacial oxide layer without causing defect to the substrate surface.